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general description the max5042/max5043 isolated multimode pwm power ics feature integrated switching power mosfets con- nected in a voltage-clamped, two-transistor, power-circuit configuration. these devices operate from a wide 20v to 76v input voltage range. the max5042 includes a hot- swap controller for use with an external power mosfet to limit inrush current for applications where the power sup- ply is plugged into a live power backplane. the max5043 does not include a hot-swap controller. the voltage-clamped power topology of the max5042/ max5043 enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. operating at up to 500khz switching fre- quency, these devices provide up to 50w of output power. the max5042/max5043 allow the implementa- tion of both forward and flyback voltage or current-mode converter topologies. a dedicated latched external shut- down provides protection in addition to internal thermal shutdown. the max5042/max5043 achieve higher efficiency when used with secondary-side synchronous rectification. these devices generate a look-ahead signal for driving secondary-side synchronous rectifiers. the max5042/max5043 are rated for operation over the -40? to +125? and -40? to +85? temperature range, respectively, and are available in a small surface- mount 56-pin thin qfn package. warning: the max5042/max5043 are designed to work with high voltages. exercise caution. applications high-efficiency telecom/datacom power supplies router/switch cards with 48v backplane power systems servers with 48v backplane power systems xdsl line cards xdsl line-driver power supplies distributed power systems with 48v bus 42v automotive power supplies power-supply modules features ? reliable single-stage clamped two-switch power ics for high efficiency ? no reset winding required ? up to 50w output power ? integrated high-voltage 75m ? power mosfets ? 20v to 76v wide input voltage range ? feed-forward voltage or current-mode control ? programmable brownout undervoltage lockout ? integrated current signal amplifier for high- efficiency, current-mode control ? internal overtemperature shutdown ? indefinite short-circuit protection ? integrated thermally protected high-voltage startup linear regulator ? integrated hot-swap controller (max5042) ? integrated look-ahead signal output drives high-speed optocoupler for secondary-side synchronous rectification ? >90% efficiency with synchronous rectification ? up to 500khz switching frequency ? high-power, small-footprint 56-pin thermally enhanced qfn package max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ________________________________________________________________ maxim integrated products 1 ordering information 19-3046; rev 2; 6/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. part temp range pin-package max5042 atn -40? to +125? 56 thin qfn max5043 etn -40? to +85? 56 thin qfn selector guide part description max5042 two-switch power ic with integrated power mosfets and hot-swap controller for isolated power supplies max5043 two-switch power ic with integrated power mosfets for isolated power supplies evaluation kit available
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pwmneg, posinpwm, drnh, xfrmrh, xfrmrl, src to negin....................-0.3v to +80v bst to negin.........................................................-0.3v to +95v bst to xfrmrh .....................................................-0.3v to +12v src to pwmneg .....................................................-0.3v to +6v reg15 to pwmneg ...............................................-0.3v to +40v reg15 to posinpwm ............................................-80v to +0.3v reg9, drvin to pwmneg ....................................-0.3v to +12v reg5 to pwmneg ...................................................-0.3v to +6v reg15 current.................................................................. 80ma reg9 current......................................................................40ma reg5 current......................................................................20ma uvlo, ramp, css, fltint, csout, rcff, rcosc to pwmneg ...............................-0.3v to +12v opto, pwmsd , sync, csp, csn, drvdel to pwmneg...........................................-0.3v to +6v ppwm to pwmneg .................................-0.3v to (reg5 + 0.3v) ppwm current .................................................................?0ma pwmpneg to pwmneg .......................................-0.3v to +0.3v drnh continuous average current (all pins combined) t j = +125?.........................................................................2a t j = +150?......................................................................1.4a xfrmrh continuous average current (all pins combined) t j = +125?.........................................................................2a t j = +150?......................................................................1.4a xfrmrl continuous average current (all pins combined) t j = +125?.........................................................................2a t j = +150?......................................................................1.4a src continuous current (all pins combined) t j = +125?.........................................................................2a t j = +150?......................................................................1.4a posinhs to negin................................................-0.3v to +80v hsen to negin........................................................-0.3v to +4v den to pwmneg .....................................................-0.3v to +4v hsgate to negin .................................................-0.3v to +12v hsdrain, hsok to negin....................................-0.3v to +80v hsok current .....................................................................20ma continuous power dissipation (t a = +70?) 56-pin thin qfn (derate 47.6mw/? above +70?) .......3.8w junction to ambient thermal resistance, ja ...............+21?/w operating temperature range MAX5042ATN ................................................-40? to +125? max5043etn ..................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? (see the absolute maximum ratings diagram below to better understand the absolute maximum ratings of the various blocks.) ic substrate, negin pwmneg, pwmpneg, hsdrain, hsok posinhs, posinpwm reg15 reg9, uvlo, ramp, css, fltint, csout, rcff, rcosc, drvin reg5, opto, pwmsd, sync, csp, csn, drvdel, src, ppwm hsen hsgate xfrmrl xfrmrh, drnh bst den 80v 80v 80v 40v 12v 6v 4v 80v 12v 4v 12v 80v 80v 95v absolute maximum ratings diagram
_______________________________________________________________________________________ 3 max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller electrical characteristics (v posinpwm = 20v to 76v, v reg15 = 18v, c reg15 = 4.7?, c reg9 = 1?, c reg5 = 1?, r rcosc = 24k ? , c rcosc = 100pf, c bst = 0.22?, r drvdel = 10k ? , c drvdel = 0.22?, v css = v csp = v csn = v ramp = v pwmneg = v negin = 0, t a = t min to t max , unless otherwise noted. typical values are at v posinpwm = 48v, t a = +25?, unless otherwise noted. all voltages are referred to pwmneg, unless otherwise noted.) parameter symbol conditions min typ max units input supply range v posinpwm 20 76 v reg15 regulator reg15 output voltage range v reg15 v posinpwm = 20v to 76v 13.0 16.6 v reg15 output voltage load regulation v posinpwm = 20v, i reg15 = 0 to 80ma 1.5 v reg15 output current inferred from load regulation test 80 ma reg15 current limit reg15 shorted to pwmneg with 10 ? reg9 regulator reg9 output voltage range v reg15 = 18v to 40v 8.3 10.1 v reg9 output voltage load regulation i reg9 = 0 to 40ma 0.35 v reg9 output current inferred from load regulation test 40 ma reg9 current limit reg9 shorted to pwmneg with 10 ? reg5 regulator reg5 output voltage range v reg15 = 18v to 40v 4.5 5.5 v reg5 output voltage load regulation i reg5 = 0 to 20ma 0.35 v reg5 output current inferred from load regulation test 20 ma reg5 current limit reg5 shorted to pwmneg with 10 ? 40 ma pwm comparator common-mode range v cm-pwm 0 5.5 v input offset voltage 10 mv input bias current -2.5 +2.5 ? propagation delay 50mv overdrive, 0 v cm-pwm 5.5v 70 ns rcosc oscillator pwm period t osc-pwm 3.9 ? maximum duty cycle 47 % maximum rcosc frequency f rcosc 1.2 mhz rcosc peak trip level v th 2.55 v rcosc valley trip level 0.2 v rcosc input bias current -0.3 ? rcosc discharge mosfet r ds(on) sinking 10ma 60 120 ? rcosc discharge pulse width 50 ns sync high level 3.5 v sync low level 0.8 v
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (v posinpwm = 20v to 76v, v reg15 = 18v, c reg15 = 4.7?, c reg9 = 1?, c reg5 = 1?, r rcosc = 24k ? , c rcosc = 100pf, c bst = 0.22?, r drvdel = 10k ? , c drvdel = 0.22?, v css = v csp = v csn = v ramp = v pwmneg = v negin = 0, t a = t min to t max , unless otherwise noted. typical values are at v posinpwm = 48v, t a = +25?, unless otherwise noted. all voltages are referred to pwmneg, unless otherwise noted.) parameter symbol conditions min typ max units sync leakage current ? ? sync maximum frequency f sync 2.4 mhz sync on-time 50 ns sync off-time 200 ns pwm logic pwm comparator propagation delay 70 ns ppwm to xfrmrl delay ppwm rising 120 ns drvdel reference voltage 1.14 1.38 v ppwm output high sourcing 2ma 2.8 v ppwm output low sinking 2ma 0.4 v pwmsd logic high 3.5 v pwmsd logic low 0.8 v pwmsd leakage current ? ? soft-start soft-start current i css 33 ? minimum opto voltage css = 0, sinking 2ma 1.4 v ramp generator minimum rcff voltage rcff sinking 2ma 2.1 v rcff leakage ?.1 1 a overload fault fltint pulse current i fltint 80 ? fltint trip point 2.0 2.7 3.5 v fltint hysteresis 0.75 v internal power fets on-resistance r dson v d r v i n = v bs t = 9v , v x f rm rh = v s r c = 0, i ds = 190ma 75 200 m ? off-state leakage current 10 ? total gate charge per fet inferred from supply current with v d s = 50v 45 nc high-side driver low-to-high latency driver delay until fet v gs reaches 0.9 x (v bst - v xfrmrh ) 80 ns high-to-low latency driver delay until fet v gs reaches 0.1 x (v bst - v xfrmrh ) 45 ns output drive voltage bst to xfrmrh with high side on 8 v low-side driver low-to-high latency driver delay until fet v gs reaches 0.9 x v drvin 80 ns
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller _______________________________________________________________________________________ 5 electrical characteristics (continued) (v posinpwm = 20v to 76v, v reg15 = 18v, c reg15 = 4.7?, c reg9 = 1?, c reg5 = 1?, r rcosc = 24k ? , c rcosc = 100pf, c bst = 0.22?, r drvdel = 10k ? , c drvdel = 0.22?, v css = v csp = v csn = v ramp = v pwmneg = v negin = 0, t a = t min to t max , unless otherwise noted. typical values are at v posinpwm = 48v, t a = +25?, unless otherwise noted. all voltages are referred to pwmneg, unless otherwise noted.) parameter symbol conditions min typ max units high-to-low latency driver delay until fet v gs reaches 0.1 x v drvin 45 ns current-sense comparator current-limit-comparator threshold voltage 140 156 172 mv current-limit-comparator propagation delay 10mv overdrive 40 ns current-sense amplifier current amplifier gain v csn = 0, v csp = 0 to 0.35v 9.75 10 10.25 v/v input voltage offset v cn = v csp = -0.3v to +0.3v 185 200 230 mv input common-mode range -0.3 +0.3 v input differential-mode range inferred from current amplifier gain test 0.35 v csp input bias current v csp = -0.3v to +0.3v, v csn = 0 -160 -40 ? csn input bias current v csp = -0.3v to +0.3v, v csn = 0 -160 -30 ? settling time v csn = 0, v csp steps from 0 to 0.2v, 10% settling time, c l = 20pf 70 ns 3db bandwidth 7mhz boost voltage circuit qb r ds(on) sinking 100ma 10 20 ? driver output delay 200 ns one-shot pulse width 300 ns thermal shutdown shutdown temperature temperature rising 150 ? thermal hysteresis 14.5 ? pwm converter undervoltage lockout (uvlo) preset uvlo threshold measured at posinpwm rising 28 31 34 v uvlo threshold hysteresis 3v uvlo resistance looking into uvlo 30 75 k ? uvlo trip point measured at uvlo rising 1.15 1.27 1.39 v uvlo hysteresis +127 mv preset den threshold max5043 only, measured at posinpwm rising 27 34 v den threshold hysteresis max5043 only 3.1 v den startup delay max5043 only 3.5 12 27.0 ms den turn-off delay max5043 only 0.2 0.7 1.5 ms den trip point max5043 only, rising with respect to pwmneg 1.11 1.35 v
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 6 _______________________________________________________________________________________ electrical characteristics (continued) (v posinpwm = 20v to 76v, v reg15 = 18v, c reg15 = 4.7?, c reg9 = 1?, c reg5 = 1?, r rcosc = 24k ? , c rcosc = 100pf, c bst = 0.22?, r drvdel = 10k ? , c drvdel = 0.22?, v css = v csp = v csn = v ramp = v pwmneg = v negin = 0, t a = t min to t max , unless otherwise noted. typical values are at v posinpwm = 48v, t a = +25?, unless otherwise noted. all voltages are referred to pwmneg, unless otherwise noted.) parameter symbol conditions min typ max units den hysteresis max5043 only 124 mv den input resistance max5043 only, looking into den 18 55 k ? supply current from v posinhs = v posinpwm = 76v, css shorted to pwmneg, reg15 = 18v 23 from reg15 = 18v, v posinhs = v posinpwm = 76v, css shorted to pwmneg 6 8.5 supply current from reg15 = 18v, v posinhs = v posinpwm = 76v, v drnh = v xfrmrh = v xfrmrl = v src = 0v 20 ma standby supply current max5042 only, v posinhs = v posinpwm = v pwmneg = v pwmpneg = v hsdrain = 76v, hsen = negin 0.6 1 ma hot-swap controller (max5042 only) hot-swap uvlo threshold posinhs with respect to negin, voltage rising 27 34 v hot-swap uvlo hysteresis 3.1 v hot-swap uvlo resistance looking into hsen 18 55 k ? startup delay from hsen rising to hsok falling 50 165 350 ms hsen turn-off delay from hsen falling to hsok rising 3 10 25 ms hsok output-high leakage current ? ? hsen reference threshold rising with respect to negin 1.11 1.35 v hsen hysteresis 124 mv hsok output low voltage sinking 5ma 0.4 v hsgate voltage high 7.5 10.0 v hot-swap slew rate c l = 10?, from hsdrain to negin 10 v/ms
_______________________________________________________________________________________ 7 max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller hot-swap undervoltage lockout threshold vs. temperature max5042 toc01 temperature ( c) hot-swap undervoltage lockout threshold (v) 100 75 50 25 0 -25 27 28 29 30 31 32 26 -50 125 v posinhs rising v posinhs falling hot-swap startup delay vs. temperature max5042 toc02 temperature ( c) hot-swap startup delay (ms) 100 75 50 25 0 -25 155 160 165 170 175 150 -50 125 hot-swap gate voltage vs. input voltage max5042 toc03 input voltage (v) hot-swap gate voltage (v) 70 60 50 40 30 8.70 8.71 8.72 8.73 8.69 20 80 hot-swap startup waveform max5042 toc04 ov ov v hsgate 5v/div 10ms/div ov v hsdrain 20v/div v hsok 20v/div 100k ? pullup pwm undervoltage lockout threshold vs. temperature max5042 toc05 temperature ( c) pwm uvlo threshold (v) 100 75 50 25 0 -25 27 28 29 30 31 32 26 -50 125 v posinpwm rising v posinpwm falling posinpwm input current, reg15 input current vs. temperature max5042 toc06 temperature ( c) supply current (ma) 100 75 -25 0 25 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 -50 125 i reg15 , v posinpwm = 76v i posinpwm , v posinpwm = 76v v reg15 = 18v, css = 0, xfrmrh = 0, no switching posinpwm input current, reg15 input current vs. input voltage max5042 toc07 input voltage (v) supply current (ma) 70 60 50 40 30 1 2 3 4 5 6 0 20 80 i reg15 i posinpwm v reg15 = 18v, css = 0, xfrmrh = 0, no switching operating frequency vs. temperature max5042 toc08 temperature ( c) operating frequency (khz) 100 75 50 25 0 -25 250 270 290 310 330 350 230 -50 125 r rcosc = 25k ? , c rcosc = 100pf r rcosc = 19k ? , c rcosc = 100pf typical operating characteristics (v posinpwm = 20v, t a = +25?, unless otherwise noted.)
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v posinpwm = 20v, t a = +25?, unless otherwise noted.) maximum duty cycle vs. temperature max5042 toc09 temperature ( c) maximum duty cycle (%) 100 75 50 25 0 -25 47 48 49 50 46 -50 125 measured at xfrmrl reg15 voltage vs. reg15 load current max5042 toc10 reg15 load current (ma) v reg15 (v) 60 40 20 14.2 14.4 14.6 14.8 15.0 14.0 080 reg15 voltage vs. input voltage max5042 toc11 input voltage (v) v reg15 (v) 70 60 50 40 30 14.4 14.5 14.6 14.7 14.8 14.9 15.0 14.3 20 80 reg9 voltage vs. reg9 load current max5042 toc12 reg9 load current (ma) v reg9 (v) 30 20 10 9.05 9.10 9.15 9.20 9.25 9.30 9.00 040 v reg15 = 20v reg9 output voltage vs. reg15 voltage max5042 toc13 reg15 voltage (v) v reg9 (v) 35 30 25 9.1 9.2 9.3 9.4 9.0 20 40 v posinpwm = 48v reg5 voltage vs. reg5 load current max5042 toc14 reg5 load current (ma) v reg5 (v) 16 12 8 4 4.8 4.9 5.0 5.1 4.7 020 v reg15 = 20v reg5 output voltage vs. reg15 voltage max5042 toc15 reg15 voltage (v) v reg5 (v) 35 30 25 4.98 4.99 5.00 5.01 5.02 4.97 20 40 v posinpwm = 48v soft-start current vs. temperature max5042 toc16 temperature ( c) soft-start current ( a) 100 75 50 25 0 -25 28 29 30 31 32 33 27 -50 125 minimum rcff level, minimum opto level vs. temperature max5042 toc17 temperature ( c) v opto , v rcff (v) 100 75 50 25 0 -25 0.5 1.0 1.5 2.0 2.5 3.0 0 -50 125 v rcff v opto i pullup into opto and rcff = 2ma, css = 0
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller current-limit threshold vs. temperature max5042 toc18 temperature ( c) current-limit threshold (mv) 100 75 50 25 0 -25 152 154 156 158 160 150 -50 125 current-limit propagation delay vs. temperature max5042 toc19 temperature ( c) current-limit propagation delay (ns) 100 75 50 25 0 -25 110 120 130 140 150 160 170 100 -50 125 measured from csp rising to xfrmrl rising cpwm propagation delay vs. temperature max5042 toc20 temperature ( c) cpwm propagation delay (ns) 100 75 50 25 0 -25 100 120 140 160 180 80 -50 125 measured from ramp rising to xfrmrl rising ppwm to xfrmrl skew vs. r drvdel max5042 toc21 r drvdel (k ? ) ppwm to power pulse skew (ns) 70 60 50 40 30 20 140 180 220 260 300 100 10 80 measured from ppwm rising to xfrmrl falling csa offset vs. temperature max5042 toc22 temperature ( c) csa offset (mv) 100 75 50 25 0 -25 205 210 215 220 200 -50 125 fault integration current vs. temperature max5042 toc23 temperature ( c) fault integration current ( a) 100 75 50 25 0 -25 76 77 78 79 80 75 -50 125 fault integration shutdown voltage vs. temperature max5042 toc24 temperature ( c) fault integration shutdown voltage (v) 100 75 50 25 0 -25 2.5 2.6 2.7 2.8 2.4 -50 125 fault integration restart voltage vs. temperature max5042 toc25 temperature ( c) fault integration restart voltage (v) 100 75 50 25 0 -25 1.85 1.90 1.95 2.00 1.80 -50 125 power fets on-resistance vs. temperature max5042 toc26 temperature ( c) power fets on-resistance ( ? ) 100 75 50 25 0 -25 60 80 100 120 140 40 -50 125 high-side fet low-side fet typical operating characteristics (continued) (v posinpwm = 20v, t a = +25?, unless otherwise noted.) _______________________________________________________________________________________ 9
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 10 ______________________________________________________________________________________ pin description pin max5042 max5043 name function 1, 2, 14, 15, 40, 42?5, 56 1, 2, 14, 15, 40, 42?5, 56 n.c. no connection. not internally connected. 3 3 rcff voltage-mode pwm ramp. connect a resistor to the input supply and a capacitor to pwmneg for input voltage feed-forward. input voltage feed-forward provides instantaneous input-voltage transient rejection and constant loop gain with varying input voltage. 4 4 ramp pwm ramp input. for voltage-mode control, connect ramp to rcff. for current- mode control, connect ramp to csout, the output of the current-sense amplifier. 5 5 opto inverting input of the pwm comparator. connect opto to the collector of the optotransistor. connect a pullup resistor from opto to reg5. 6 6 css soft-start. connect a capacitor from css to pwmneg to soft-start the converter. 7 7 bst boost-capacitor bypass for high-side mosfet gate drive. connect a 0.1? capacitor from bst to xfrmrh for the internal high-side mosfet driver. 8 8 drvin low-side mosfet driver supply. bypass drvin with a 0.22? capacitor to pwmpneg. 9 9 pwmpneg low-side mosfet driver return. connect pwmpneg externally to pwmneg with a short trace. 10 10 rcosc oscillator timing resistor and capacitor connection. connect a capacitor from rcosc to pwmneg and a resistor from rcosc to reg5. the switching frequency is half the frequency of the sawtooth signal at this connection. 11 11 fltint fault integration input. use fltint in addition to cycle-by-cycle current limit. during persistent current-limit faults, a capacitor connected to fltint charges with an internal 80? current source. switching terminates when the voltage reaches 2.7v. an external resistor connected in parallel discharges the capacitor. switching resumes when the voltage drops to 1.8v. 12 12 sync synchronization input. the switching frequency of the power supply is half the synchronization frequency, ensuring less than 50% maximum duty cycle. 13 13 pwmsd latched shutdown input. pull pwmsd low with respect to pwmneg to stop switching. to restart, release pwmsd and cycle the input supply. do not leave pwmsd unconnected. use pwmsd to prevent catastrophic secondary rectifier overheating by monitoring the temperature and issuing a shutdown command with an optocoupler. connect pwmsd to reg5 when not used. 16, 17, 20, 21, 24 16, 17, 20, 21, 24 src source connection for the internal low-side power mosfet. connect src to pwmpneg with a low-value resistor for current limiting. 18, 19, 22, 23 18, 19, 22, 23 xfrmrl low-side connection for the isolation transformer 25 posinhs hot-swap controller positive input supply (max5042 only). connect posinhs along with posinpwm to the most positive rail of the input supply.
______________________________________________________________________________________ 11 max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller pin description (continued) pin max5042 max5043 name function 26 hsok hot-swap ok (max5042 only). hsok ? open-drain output is forced to negin upon hot-swap completion. 27 hsen hot-swap enable (max5042 only). hsen is the center point of the internal hot-swap uvlo divider. use an external voltage-divider or a 100k ? pullup resistor to the most positive rail to override. 28, 29 negin negative supply input (max5042 only). negin connects to the most negative input supply rail. negin provides the hot-swap circuit? most negative connection. negin is at the same potential as the ic substrate. 30 hsgate hot-swap gate (max5042 only). connect hsgate to the gate of the external hot- swap mosfet. 31 hsdrain hot-swap mosfet drain sense (max5042 only). connect hsdrain to the drain of the external hot-swap mosfet. 32 32 csout current-sense amplifier output. the amplifier has a gain of 10. connect csout to ramp for current-mode control. 33 33 csp positive current-sense connection. place the current-sense resistor as close as possible to the device and use a kelvin connection. 34 34 csn negative current-sense connection. place the current-sense resistor as close as possible to the device and use a kelvin connection. 35 26, 28, 29, 31, 35 pwmneg analog signal return for the pwm section 36 36 drvdel driver delay adjust connection. connect a resistor and a 0.22? capacitor from drvdel to pwmneg. the resistor at drvdel controls the skew between the ppwm signal and the power pulse applied to the internal power mosfets. use in conjunction with a secondary-side synchronous-rectifier controller. the skew allows for the optimization of the synchronous-rectifier drive pulse. 37 37 ppwm pwm pulse output. ppwm leads the internal power mosfet pulse by an amount determined with the resistor value at drvdel. 38 38 reg9 9v internal regulator output. use primarily as a source for the internal gate drivers. bypass reg9 to pwmneg with a 1? ceramic capacitor. 39 39 reg5 5v internal regulator output. bypass reg5 to pwmneg with a 1? ceramic capacitor. 41 41 reg15 15v startup regulator output. a voltage greater than 18v on reg15 disables the regulator. bypass reg15 to pwmneg with at least one 1? ceramic capacitor. 46 46 uvlo pwm undervoltage lockout. uvlo is the center point of the pwm undervoltage lockout divider. use an external divider or a 100k ? pullup resistor to posinpwm to override. connect the external resistor-divider network from posinpwm to pwmneg.
max5042/max5043 detailed description the max5042/max5043 pwm multimode power ics are designed for the primary side of voltage or current- mode isolated, forward or flyback power converters. these devices provide a high degree of integration aimed at reducing the cost and pc board area of isolat- ed output power supplies. use the max5042/max5043 primarily for 24v, 42v, or 48v power bus applications. the max5042/max5043 provide a complete system capable of delivering up to 50w of output power. the max5042 contains a hot-swap controller in addition to the pwm and power mosfets. the hot-swap section requires an external mosfet (qhs). figure 1 details the max5042 conceptual block diagram. c in represents the input bulk storage capacitance of the pwm circuit that requires the soft-start to reduce the inrush current from the backplane. when input power is applied, capacitor c in is completely discharged and qhs is off. an applied voltage higher than the default undervoltage lockout threshold of the hot-swap controller (30.5v) for more than 165ms (internal turn-on delay) causes the gate voltage of qhs to start gradually increasing. this results in a controlled slew-rate turn-on. the drain volt- age of qhs falls at a rate of approximately 10v/ms, drawing a current load from the backplane of approxi- mately 1a for each 100? of c in capacitance. the max5042? pwm block is prevented from starting up until the qhs mosfet is fully enhanced. after qhs completely turns on and the voltage across capacitor c in is above the default startup voltage (31v) of the pwm section, the hot swap enables the pwm block and the soft-start cycle begins. soft-start limits the amount of current initially drawn from the primary during startup and also prevents possible output-voltage overshoots. the max5043, detailed in figure 2, does not contain an integrated hot-swap controller. the max5043 begins operating when the input voltage exceeds both of the undervoltage lockout voltages (at uvlo and den pins) for 10ms. the max5042/max5043 support both forward and fly- back power topologies. in forward mode, the maximum output power is approximately 50w. in flyback mode, the maximum output power is approximately 20w. the amount of power dissipated by the package limits the output power. the max5042/max5043? qfn package features an exposed metal pad on the bottom of the package. solder the exposed pad directly to the most negative supply in the system. use a large copper area to improve heat dissipation. facilitate heat transfer with thermal vias. two-switch power ics with integrated power mosfets and hot-swap controller 12 ______________________________________________________________________________________ pin description (continued) pin max5042 max5043 name function 47 25, 47 posinpwm pwm analog positive-supply input. connect posinpwm to the most positive input supply rail. 48, 51, 54, 55 48, 51, 54, 55 drnh drain connection of the internal high-side pwm power mosfet. connect drnh to the most positive rail of the input supply. 49, 50, 52, 53 49, 50, 52, 53 xfrmrh high-side connection for the isolation transformer ?7den delayed enable input (max5043 only). den is the center point of the delayed enable divider. use an external voltage-divider or a 100k ? pullup resistor to the most positive rail to override. 30 n.c. no connection (max5043 only). leave unconnected. pwm circuit with integrated fets integrated hot-swap controller qh ql qhs external hot-swap fet pwmneg, pwmpneg t1 c in l c out +v posinpwm negin max5042 bulk storage capacitor (hot-swapped capacitor) v out figure 1. simplified diagram of a max5042-based isolated power supply
set the switching frequency with a resistor and a capacitor at rcosc. switching at 250khz ensures switching losses are minimal and external power pas- sives are small enough for a compact circuit. the max5042/max5043 incorporate an advanced set of protection features that make them uniquely suitable when high reliability and comprehensive fault protection are required, as in telecommunication equipment power- supply applications. the max5042/max5043 15v linear regulator output powers the 9v and 5v regulators used to drive the gates and internal circuitry. a tertiary winding connects to reg15 through a rectifier to power the device after startup and reduces power dissipation in the max5042/max5043 package. when reg15 is externally powered, the internal 15v regulator is disabled. figures 3 and 4 show the block diagrams of the max5042 and max5043, respectively. the power-ok signals from the hot-swap section, regulators, thermal shutdown, and uvlo combine to generate the internal shutdown signal shdn. when asserted, shdn disables the comparators and oscillator. deasserting shdn releases the compara- tors and oscillators. the falling edge of shdn is delayed allowing the internal signals to settle before the pwm puls- es appear. during the time between the falling edge of shdn and its delayed signal, the 10 ? internal mosfet (qb) from xfrmrh to pwmpneg turns on, charging the bst capacitor. after startup, this mosfet also turns on for approximately 300ns at each half period to help charge the bst capacitor. power topology the two-switch forward-converter topology offers out- standing robustness against faults and transformer satu- ration while affording efficient use of the integrated 75m ? power mosfets. voltage-mode control with feed- forward compensation allows the rejection of input sup- ply disturbances within a single cycle similar to that of current-mode controlled topologies. this control method offers some significant benefits when compared with current-mode control. these benefits include: no minimum duty-cycle requirement due to current- signal filtering or blanking. clean modulator ramp and higher amplitude for increased stability. stable bias point of the optocoupler led and photo- transistor for maximized control-loop bandwidth (in current-mode applications, the optocoupler bias point is output-load dependent). predictable loop dynamics simplifying the design of the control loop. the two-switch power topology recovers energy stored in both the magnetizing and parasitic leakage induc- tances of the transformer. figure 7 shows the schemat- ic diagram of a 48v input and 5v, 8a output isolated power supply built with the max5042. the max5042/max5043 also support current-mode con- trol. current-mode control has advantages such as a sin- gle-pole power circuit and a small-signal transfer function that simplify the design of power supplies with widely varying output capacitors. undervoltage lockout the max5042 has two uvlo functions. both the hot- swap section and the pwm section contain their own undervoltage lockout comparators (hsen and uvlo, respectively). the max5043 lacks the hot-swapping function, but retains the pwm uvlo and the deglitched undervoltage lockout/power-on reset. in both cases, internal resistors set a default input-voltage enable threshold of 31v (typ). the pwm default input voltage threshold value can be adjusted by using an external divider in parallel with the internal divider. the tolerances of the external divider resistors dominate the precision of the uvlo trip point if their values are smaller than those of the internal divider. override the default threshold by using: r rrr vv vrrrrrvv he le li hi in ref ref hi li le le li in ref = () + () () - -- max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ______________________________________________________________________________________ 13 pwm circuit with integrated fets qh ql t1 l c out c in +v posinpwm pwmneg max5043 bulk storage capacitor v out figure 2. simplified diagram of a max5043-based isolated power supply
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 14 ______________________________________________________________________________________ reg5 (5v) reg5 ok reg9 (9v) ref (1.25v) reg9 ok reg15 ok reg15 ok reg5 ok reg15 (15v) ovt ref ok uvlo 1.25v 1.125v 1.2m ? 7.5v 50k ? d r q 7.5v pwmneg 7.5v pwmneg 5v 32 a 5v 80 a cpwm iflt "1" ovrld 2.3v/1.6v cuvlo r s q uvlo ovt uvlo refok reg15ok reg9ok reg5ok ovrld r s q r q t-ff clk shdn osc leading- edge delay level shift res qh 0.1 ? qb 10 ? leading- edge delay one shot ql 0.1 ? ovt thermal shutdown +150 c 12 c hysteresis ilim 10mhz 150mv iamp 200mv hot-swap control logic 40 ? 80v, dmos 840k ? 35k ? 3v 460k ? level shift to pwm hot-swap section max5042 41 39 38 3 11 reg15 reg5 reg9 rcff fltint 4 5 6 35 13 ramp opto css pwmneg pwmsd 32 25 27 28 csout posinhs hsen negin (29) 26 30 31 34 33 12 10 9 16 hsok hsgate hsdrain csn csp sync rcosc pwmpneg src (17, 20, 21, 24) 18 8 49 48 7 36 37 xfrmrl (19, 22, 23) drvin xfrmrh (50, 52, 53) drnh (51, 54, 55) bst drvdel ppwm 46 47 uvlo posinpwm gain = 10 pwmneg figure 3. block diagram of the max5042 power ic
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ______________________________________________________________________________________ 15 reg5 (5v) reg5 ok reg9 (9v) ref (1.25v) reg9 ok reg15 ok reg15 ok reg15 (15v) ovt ref ok uvlo 1.25v 1.125v 1.2m ? 7.5v 50k ? d r q 7.5v 3 ? pwmneg 7.5v 50 ? pwmneg 5v 32 a 5v 80 a cpwm iflt "1" ovrld 2.3v/1.6v cuvlo r s q uvlo ovt uvlo refok reg15ok reg9ok reg5ok ovrld r s q r q t-ff clk shdn osc leading- edge delay level shift res qh 0.1 ? qb 10 ? leading- edge delay one shot ql 0.1 ? ovt thermal shutdown +150 c 12 c hysteresis ilim 10mhz 150mv iamp 200mv 840k ? 35k ? 3v max5043 41 39 38 3 11 reg15 reg5 reg9 rcff fltint 4 5 6 35 13 ramp opto css pwmneg (26) pwmsd 32 25 27 28 csout posinpwm den pwmneg (29, 31) 34 33 12 10 9 16 csn csp sync rcosc pwmpneg src (17, 20, 21, 24) 18 8 49 48 7 36 37 xfrmrl (19, 22, 23) drvin xfrmrh (50, 52, 53) drnh (51, 54, 55) bst drvdel ppwm 46 47 uvlo posinpwm gain = 10 cden 1.25v 1.125v 10ms delay pwmneg reg5 ok figure 4. block diagram of the max5043 power ic
max5042/max5043 where r he is the external high-side resistor, r le is the external low-side resistor, r hi is the internal high-side resistor (1.2m ? , typ), r le is the internal low-side resistor (50k ? , typ), v ref is 1.27v (typ), and v in is the desired threshold. use an external 100k ? pullup resistor to posinpwm to override uvlo functionality for either lockout. internal regulators an internal high-voltage linear regulator provides a 15v output at reg15. this serves as the input to the 9v reg- ulator that provides bias for the internal mosfet dri- vers. the 15v regulator also provides the bias for reg5, a 5v supply used both by internal as well as external cir- cuitry. bypass the reg15, reg9, and reg5 regulators with 1? ceramic capacitors. a voltage greater than 18v and less than 40v on reg15 disables the internal high- voltage startup regulator. the reg9 regulator steps down the voltage on reg15 to an output of 9v with a current limit of 100ma. the reg5 regulator steps down the voltage on reg15 to an output of 5v with a current limit of 40ma. disabling the reg15 regulator by power- ing reg15 with an external power supply considerably reduces the internal power dissipation in the max5042/max5043. the voltage and power necessary to override the reg15 internal regulator can be generat- ed with a rectifier and an extra winding from the main transformer. soft-start program the max5042/max5043 soft-start with an external capacitor between css and pwmneg. when the device turns on, the soft-start capacitor (c css ) charges with a constant current of 33?, ramping up to 7.3v. during this time, opto is clamped to css + 0.6v. this initially holds the duty cycle lower than the value the regulator tries to impose, limiting the current inrush and the voltage overshoot at the secondary. when the max5042/max5043 turn off, the soft-start capacitor internally discharges to pwmneg. secondary-side synchronization the max5042/max5043 provide convenient synchro- nization of the secondary-side synchronous rectifiers. figure 5 shows the connection diagram with a high- speed optocoupler. choose an optocoupler with a propagation delay of less than 50ns. for optimum results, adjust the resistor connected to drvdel to provide the required amount of delay between the leading edge of the ppwm signal and the turn-on of the power mosfets. use the following formu- la to calculate the approximate resistance (r drvdel ) required to set the delay between the ppwm and the power pulse applied to the transformer: where t drvdel is the required delay from the rising edge of ppwm to the switching of the internal power mosfets. pwm regulation the max5042/max5043 are multimode pwm power ics supporting both voltage and current-mode control. voltage-mode control and the pwm ramp for voltage-mode control, the feed-forward pwm ramp is generated at rcff. from rcff connect a capacitor to pwmneg and a resistor to posinpwm. the ramp generated is applied to the noninverting input of the pwm comparator at ramp and has a minimum voltage of 1.5v to 2.5v. the slope of the ramp is determined by the voltage at posinpwm and affects the overall loop gain. the ramp peak must remain below the dynamic range of rcff (0 to 5.5v). assuming the maximum duty cycle approaches 50% at a minimum input voltage (pwm uvlo turn-on threshold), use the following for- mula to calculate the minimum value of either the ramp capacitor or resistor: where: v inuvlo = the minimum input supply voltage (typically the pwm uvlo turn-on voltage), f s = the switching frequency, v r p-p = the peak-to-peak ramp voltage (2v, typ). rc v fv rcff rcff inuvlo srpp 2 - rt ns k ns drvdel drvdel =? () () ? ? ? ? ? ? 100 2 ? two-switch power ics with integrated power mosfets and hot-swap controller 16 ______________________________________________________________________________________ drvdel pwmneg ppwm max5042/max5043 r1 c1 0.22 f r2 c2 5v ps9715 or equivalent high-speed optocoupler figure 5. secondary-side synchronous rectifier driver using a high-speed optocoupler
maximize the signal-to-noise ratio by setting the ramp peak as high as possible. calculate the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the pwm comparator to the output) using the following formula: g ps = n sp ? r rcff ? c rcff ? f s where n sp = the secondary to primary power transformer turns ratio. current-sense amplifier and current-mode control the max5042/max5043 can also be programmed for current-mode control (see figure 6). this control method offers beneficial advantages for certain appli- cations. current-mode control reduces the order of the output filter, allowing easier control-loop compensation. in current-mode control, the voltage across the current- sense resistor at src is amplified by the internal gain- of-10 amplifier iamp. the cycle-by-cycle current-limit threshold is 156mv. this is the peak voltage amplified by iamp. a 200mv offset is added to this voltage. the voltage at the output of the current-sense amplifier is: v csout = 2 + 10(v csp - v csn ) the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the pwm comparator to the output) can be calculated using the following formula: where n ps = the primary to secondary power trans- former turns ratio, r l = the low-frequency output impedance, r sense = the primary current-sense resistor value. oscillator and synchronization program the max5042/max5043 oscillator using an rc network at rcosc with the resistor connected to reg5 and the capacitor connected to pwmneg. the pwm frequency is half the frequency at rcosc. use the following formula to calculate the oscillator components: where c pcb = 14pf, reg5 = 5v, f s = switching frequency, v th = rcosc peak trip level. the delay programmed by the resistor at drvdel lim- its the power mosfet? maximum duty cycle to less than 50 percent. sync allows synchronization of the max5042/max5043 to an external clock. for proper synchronization, set the external sync frequency 15% to 20% higher than the programmed free-running frequency of the max5042/ max5043? internal oscillator. the actual switching frequency will be half the synchronizing frequency. integrating fault protection the integrating fault protection feature allows the max5042/max5043 to ignore transient overcurrent conditions for a programmable amount of time, giving the power supply time to behave like a current source to the load. this can happen, for example, under load- current transients when the control loop requests maxi- mum current to keep the output voltage from going out of regulation. program the ignore time externally by connecting a capacitor to fltint. under sustained overcurrent faults, the voltage across this capacitor ramps up toward the fltint shutdown threshold (typi- cally 2.7v). when fltint reaches the threshold, the power supply shuts down. a high-value bleed resistor connected in parallel with the fltint capacitor allows the capacitor to discharge toward the restart threshold (typically 1.8v). crossing the restart threshold soft- starts the supply again. the ilim comparator provides cycle-by-cycle current limiting with a typical threshold of 156mv. the fault inte- gration circuit works by forcing an 80? current out of fltint for one clock cycle every time the current-limit comparator (figures 3 and 4, ilim) trips. use the fol- lowing formula to calculate the approximate capaci- tance (c fltint ) needed for the desired shutdown time. r fc c v vv rcosc s rcosc pcb reg reg th ln = + () ? ? ? ? ? ? ? 1 2 5 5 gn r r ps ps l sense = max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ______________________________________________________________________________________ 17 csp pwmneg csn pwmpneg src ramp csout opto max5042/max5043 rs 50m ? (approximately 35w to 40w) figure 6. simplified connection diagram for current-mode control
max5042/max5043 where i fltint = 80?, t sh is the desired ignore time during which current-limit events from the current-limit comparator are ignored. some testing may be required to fine tune the actual value of the capacitor. calculate the approximate bleed resistance (r fltint ) needed for the desired recovery time using the follow- ing formula: where t rt is the desired recovery time. choose at least t rt = 10 x t sh . typical values for t sh range from a few hundred microseconds to a few mil- liseconds. shutdown modes latched shutdown the max5042/max5043 feature a latched shutdown that terminates switching in the event of a serious fault. external faults in synchronously rectified power supplies cause a loss of control for the rectifiers. either the body or the external schottky diodes conduct, resulting in a very high power dissipation and a quick rise of the power-sup- ply temperature. a thermal sensor placed on the same ground plane as the secondary-side rectifiers can sense this catastrophic increase in temperature and issue a shutdown signal to pwmsd . asserting pwmsd stops switching and latches the fault until the power is cycled. connect pwmsd to reg5 to disable latched shutdown. functional shutdown shut down the max5042/max5043 by pulling uvlo to pwmneg using an open-collector or open-drain transis- tor connected to pwmneg. pulling hsen to negin also shuts down the max5042 after a 10ms turn-off delay. pulling den low also shuts down the max5043 with a 1ms turn-off delay. when hsen is used, the max5042 goes through a full hot-swap startup sequence with a 165ms startup delay. the max5043 also has a 10ms delay from when den asserts. thermal shutdown the max5042/max5043 feature internal thermal shut- down. internal sensors monitor the high-power areas. thermal faults arise from excessive dissipation in the power fets or in the regulators. when the temperature limit is reached, switching is terminated and the regulator shuts down. the integration of thermal shutdown and the power mosfets result in a very robust power circuit. max5042 hot-swap controller the max5042 integrates a pwm power ic with a hot- swap controller. the design allows a power supply built around the max5042 to be safely hot-plugged into a live backplane without causing a glitch on the power- supply rail. the hot-swap section operates from posinhs to negin. the max5042 only requires an external n-channel mosfet to provide hot-swap con- trol. figures 1 and 3 detail hot-swap functionality. the max5042 controls an external n-channel power mosfet placed in the negative power-supply pathway. when power is applied, the max5042 keeps the mos- fet off. the mosfet remains off indefinitely if hsen is below 1.26v, posinhs is below the undervoltage lock- out level (31v), or the die temperature exceeds +150?. if none of these conditions exist for 165ms, the max5042 gradually turns on the mosfet, allowing the voltage on hsdrain to fall no faster than 10v/ms. during this period, the pwm block remains in shut- down. the inrush current through the external mosfet (and therefore through the capacitor c in ) is limited to a level proportional to its capacitance, and the constant hsdrain slew rate. after the mosfet completely turns on, and hsdrain falls to its final value, the hot-swap period is terminated and the pwm section of the ic powers up. hsen offers external control of the max5042, facilitat- ing power-supply sequencing. hsen can also be used to change the undervoltage lockout level using an external divider network, if necessary. undervoltage lockout keeps the external hot-swap mosfet switched off as long as the magnitude of the input voltage is below the desired level. there is a 10ms turn-off delay on the hsen signal. a power-good output, hsok , asserts when the external mosfet completely turns on. hsok is an open-drain output referenced to negin, and can withstand up to 80v above negin. r t c fltint rt fltint ln . . ? ? ? ? ? ? ? 23 16 c it fltint fltint sh . ? 14 two-switch power ics with integrated power mosfets and hot-swap controller 18 ______________________________________________________________________________________
determining hot-swap inrush current calculate the hot-swap inrush current using the follow- ing formula: where: c in = the load capacitance, s hslr is the max5042 hot-swap slew rate magnitude given in the electrical characteristics table. for example, assuming an input bulk capacitance of 100?, and using the typical value of 10v/ms for the slew rate, the calculated inrush current is 1a. see table 1 for suggested external hot-swap mosfets. ic dv dt cs cin hsdrain in hslr in == max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ______________________________________________________________________________________ 19 table 1. max5042 suggested external hot-swap mosfets maximum i load (a) suggested external mosfet 0.25 irfl110 0.5 irfl4310 1 irfr3910 2 irf540ns 3 irf1310ns 4 irf1310ns ramp rcff reg9 drvin fltint drvdel sync pwmsd reg5 r22 10k ? c25 0.22 f r20 10k ? r14 10k ? r13 1m ? c12 0.1 f c3 1 f c9 220pf r12 200k ? 1% c20 0.1 f 100v c1 220 f 100v c30 0.68 f 100v v in+ 32v to 72v negin c13 1 f r15 24.9k ? 1% c14 100pf rcosc c11 0.1 f css n1 (hot-swap mosfet) negin hsgate hsdrain pwmneg, csn pwmpneg opto r21 1.24k ? 1% max5042 c6 0.1 f bst xfrmrh xfrmrl c7 1 f r9 15 ? d4 r10 33m ? 1% d1 d2 reg15 csp, src posinpwm hsen drnh uvlo r6 200 ? 1% c8 0.33 f r11 20 ? 1% c16 0.001 f c5 0.0047 f d3 l1 4.4 h c17 150 f 6.3v c18 150 f 6.3v c4 0.1 f 5v 8a sgnd r1 25.5k ? 1% r2 8.25k ? 1% r5 10 ? 1% r4 10 ? c15 0.1 f c19 0.15 f r3 150 ? 1% u2 fod2712 e c led fb comp gnd u1 t1 figure 7. max5042 typical application circuit (48v power supply with hot-swap capability) typical application circuits
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller 20 ______________________________________________________________________________________ ramp rcff reg9 drvin fltint drvdel sync pwmsd reg5 r22 10k ? c25 0.22 f r20 10k ? r14 10k ? r13 1m ? c12 0.1 f c13 1 f c9 220pf r12 200k ? 1% v in+ 32v to 72v c13 1 f r15 24.9k ? 1% c14 100pf rcosc c11 0.1 f css pwmneg pwmneg, csn opto r21 1.24k ? 1% max5043 c6 0.1 f bst xfrmrh xfrmrl c7 1 f r9 15 ? d4 r10 33m ? 1% d1 d2 reg15 src, csp posinpwm drnh uvlo r6 200 ? 1% c8 0.33 f d3 l1 4.4 h c17 150 f 6.3v c18 150 f 6.3v c4 0.1 f 5v 10a sgnd r1 25.5k ? 1% r2 8.25k ? 1% r5 10 ? 1% c15 0.1 f c19 0.15 f r3 150 ? 1% u2 fod2712 e c led fb comp gnd u1 t1 pwmneg c1 220 f 100v 0.68 f 100v r4 10 ? figure 8. max5043 typical application circuit (48v power supply without hot-swap capability, this circuit has not been tested) typical application circuits (continued)
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller ______________________________________________________________________________________ 21 chip information transistor count: 35,247 process: bicmos dmos thin qfn top view exposed paddle connected to negin. exposed paddle connected to pwmneg. 52 xfrmrh 51 drnh 56 n.c. 55 drnh 54 drnh 53 xfrmrh 50 xfrmrh 49 xfrmrh 48 drnh 47 posinpwm 46 uvlo 45 n.c. 44 n.c. 43 n.c. n.c. 15 src 16 src 17 xfrmrl 18 xfrmrl 19 src 20 src 21 xfrmrl 22 xfrmrl 23 posinhs 25 src 24 hsok 26 negin 28 hsen 27 29 negin 30 hsgate 31 hsdrain 32 csout 33 csp 34 csn 35 pwmneg 37 ppwm 36 drvdel 38 reg9 39 reg5 40 n.c. 41 reg15 42 n.c. n.c. 14 pwmsd 13 sync 12 fltint 11 rcosc 10 pwmpneg 9 drvin 8 bst 7 css 6 opto 5 rcff 3 ramp 4 n.c. 2 n.c. 1 MAX5042ATN thin qfn 52 xfrmrh 51 drnh 56 n.c. 55 drnh 54 drnh 53 xfrmrh 50 xfrmrh 49 xfrmrh 48 drnh 47 posinpwm 46 uvlo 45 n.c. 44 n.c. 43 n.c. n.c. 15 src 16 src 17 xfrmrl 18 xfrmrl 19 src 20 src 21 xfrmrl 22 xfrmrl 23 posinpwm 25 src 24 pwmneg 26 pwmneg 28 den 27 29 pwmneg 30 n.c. 31 pwmneg 32 csout 33 csp 34 csn 35 pwmneg 37 ppwm 36 drvdel 38 reg9 39 reg5 40 n.c. 41 reg15 42 n.c. n.c. 14 pwmsd 13 sync 12 fltint 11 rcosc 10 pwmpneg 9 drvin 8 bst 7 css 6 opto 5 rcff 3 ramp 4 n.c. 2 n.c. 1 max5043etn pin configurations
max5042/max5043 two-switch power ics with integrated power mosfets and hot-swap controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 56l thin qfn.eps

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